EE 402 Very Large Scale Integrated System Design II Select Term:
VLSI system computer aided design (CAD) tools; laboratory experience in custom VLSI system chip design on workstations using concepts of cell hierarchy; design of large adder arrays and multipliers; VLSI architecture design; pipelining; low-power design strategies; final proje involving specification, design and evaluation of a VLSI chip or VLSI CAD program; written report and oral presentation on the final project.
SU Credits : 3.000
ECTS Credit : 6.000
Prerequisite :
Undergraduate level EE 401 Minimum Grade of D
OR Undergraduate level EL 401 Minimum Grade of D
Corequisite :
EE 402R