EE 310 Hardware Description Languages Select Term:
Introduction to hardware description languages; VHDL fundamentals, behavioral and structural models; syntax and basic rules; design entry; behavioral simulation; logic synthesis and synthesizeable code development; design mapping to standard cells and/or field programmable gate array (FPGA).
SU Credits : 3.000
ECTS Credit : 6.000
Prerequisite :
Undergraduate level CS 303 Minimum Grade of D
Corequisite :
EE 310L