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EE 310 Hardware Description Languages Select Term:
Introduction to Hardware Description Languages; Digital design, Verilog Language Elements, Structural, Dataflow, Behavioral, Hierarchical Design, Finite State Machine with Verilog, Parametrized Modules, Testbenches, Sequential Design, Numbers, Delay, Loops, Simulation vs. Synthesis, Discrete Event Simulation, FPGA, Look-Up-Tables (LUTs), Registers, Multiplexers, I/O, Synchronous vs. Asynchronous, BRAM, FIFO, DSP, Clock, Pipelining, Latency, Throughput, Design Examples, Systolic Arrays, AXI Bus, FPGA Design Process, Advanced Verilog, Verilog Classes, Model Optimizations, System Verilog Interfaces, Standard Cell and ASICs, Modern Hardware Programming with Chisel HDL, Collections, Encapsulation, Verification and UVM, Design Space Exploration
SU Credits : 3.000
ECTS Credit : 6.000
Prerequisite : Undergraduate level CS 303 Minimum Grade of D
Corequisite : EE 310L
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