HARDWARE AWARE TRAINING AND FPGA IMPLEMENTATION
OF A QUANTIZED SIMPLERNN
Kadirhan Kana
Electronics Engineering, MSc Thesis, 2026
Thesis Jury
Asst. Prof. KORKUT KAAN TOKGÖZ (Thesis Advisor)
Prof. ÖZCAN ÖZTÜRK
Assoc. Prof. ENGİN AFACAN
Date & Time: June 16th, 2026 – 2:00 PM
Place: FENS L027
Keywords: FPGA, quantized neural networks, fixed point arithmetic,
hardware-aware training, time series classification
Abstract
This thesis proposes the training of a quantized SimpleRNN model for recognizing cattle behavior based on accelerometer time series signals and its hardware realization on an Field Programmable Gate Array (FPGA) board. In this work, we propose a complete software to hardware pipeline for the implementation of a recurrent neural network model that was initially developed in software. Then, it transformed into a fixed point implementation and tested on the FPGA board. The dataset was processed to isolate four target classes: grazing (GRZ), moving (MOV), resting (RES), and ruminating (RUS). Initially, a baseline of floating point SimpleRNN was trained which resulted in 94% accuracy. Then, Post Training Quantization (PTQ) and Quantization Aware Training (QAT) approaches have been studied to deploy the model on the FPGA platform. A model quantization was performed by implementing the proposed quantized model on the Nexys A7 FPGA using ROM based architecture, UART interface, recurrent processing blocks, batch normalization with folding, ReLU6 activations and dense layers for classification. Comparison between the FPGA and software results allows to validate the classification accuracy and consistency between the two platforms. The experimental study revealed that the PTQ reached a software-hardware match rate of 33.40% while QAT reached 99.91%. The implemented design also achieved timing closure at 50 MHz within the available FPGA resource constraints.
