Course Catalog
| EE 636 Formal Specification and Verification of Digital Systems | 3 Credits | ||||||
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| This course covers major formal specification and verification approaches used in the automation of digital design. Topics include the use of logic-based formalisms, formal verification of combinatorial circuit designs, symbolic model checking, specification and verification of synchronous and asynchronous sequential circuits, compositional verification, verification of complex hardware systems. | |||||||
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| Prerequisite: __ | |||||||
| Corequisite: __ | |||||||
| ECTS Credit: 10 ECTS (10 ECTS for students admitted before 2013-14 Academic Year) | |||||||
| General Requirements: | |||||||