This course describes high performance and low power
integrated circuit (IC) design issues for advanced
nanoscale technologies. After a brief review of VLSI
design methodologies and current IC trends, fundamental
challenges related to the conventional CMOS
technologies are described. The shift from logic-centric to
interconnect-centric design is emphasized. Primary
aspects of an interconnect-centric design flow are
described in four phases: (1) general characteristics of on-
chip interconnects, (2) on-chip interconnects for data
signals, (3) on-chip power generation and distribution,
and (4) on-chip clock generation and distribution.
Existing design challenges faced by IC industry are
investigated for each phase. Tradeoffs among various
design criteria such as speed-power-noise-area are
highlighted. In the last phase of the course, several post-
CMOS devices, emerging circuit styles, and architectures
are briefly discussed. At the end of the course, the
students will have a thorough understanding of the
primary
circuit and physical level design challenges with
application to industrial IC design. )
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