Hardware Description Languages (EE 310)

2019 Spring
Faculty of Engineering and Natural Sciences
Electronics Engineering(EE)
3
8.00 / 6.00 ECTS (for students admitted in the 2013-14 Academic Year or following years)
Erdinç Öztürk -erdinco@sabanciuniv.edu,
English
Undergraduate
CS303
Formal lecture,Interactive lecture,Laboratory
Interactive,Communicative,Task based learning
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CONTENT

Introduction to hardware description languages; VHDL fundamentals, behavioral and structural models; syntax and basic rules; design entry; behavioral simulation; logic synthesis and synthesizeable code development; design mapping to standard cells and/or field programmable gate array (FPGA).

OBJECTIVE

This course teaches designing digital circuits, behavioral and RTL modeling of
digital circuits using Verilog HDL, verifying these models, and synthesizing RTL
models to standard cell libraries and FPGAs. Students gain practical experience
by designing, modeling, implementing and verifying several digital circuits.

LEARNING OUTCOME

By the end of this course, students should be able to:
Describe hardware description languages (HDL) and Verilog HDL;
Design digital circuits;
Write behavioral models of digital circuits;
Write register transfer level (RTL) models of digital circuits;
Verify behavioral and RTL models;
Describe standard cell libraries and FPGAs;
Synthesize RTL models to standard cell libraries and FPGAs;
Implement RTL models on FPGAs and verify their implementations

ASSESSMENT METHODS and CRITERIA

  Percentage (%)
Final 30
Midterm 35
Assignment 35

RECOMENDED or REQUIRED READINGS

Textbook

A Verilog HDL Primer, Jayaram Bhasker, Star Galaxy Publishing, Third Edition
Verilog HDL Synthesis: A Practical Primer, Jayaram Bhasker, Star Galaxy Publishing