EE 542 Digital Systems Verification and Testing Select Term:
This course introduces the problems of design verification and testing. It then covers the design verification process, various design errors, simulation- based verification, emulation-based verification, formal verification, timing verification. After that, the course covers the digital systems testing process, various fault models, automatic test pattern generation (ATPG), fault simulation, memory test, design for testability, built-in self-test, SoC test structures. Finally, it covers ATPG- based verification techniques.
SU Credits : 3.000
ECTS Credit : 10.000
Prerequisite : -
Corequisite : -